(i) Field of the Invention
The present invention relates to a semiconductor integrated circuit constituted by combining a plurality of transistors, a logic operation circuit, and a flip flop, and more particularly to a technique for reducing consumption power and improving a signal transmission rate.
(ii) Description of the Related Art
In order to increase the speed of a CMOS logic circuit, the circuit must be constituted by transistors with a low threshold voltage. However, when the threshold voltage of the transistors lowers, a leak electric current increases at the time of standby. To avoid this problem, there is proposed an MT (Multiple Threshold voltage)-CMOS circuit which can simultaneously achieve the high-speed operation of the circuit and the low leak electric current at the time of standby.
FIG. 9 is a conventional circuit diagram of the MT-CMOS circuit. The circuit shown in FIG. 9 includes a Low-Vth block 1 which is connected between a virtual power supply line VDD1 and a virtual ground line VSS1 and constituted by a plurality of transistors having a low threshold voltage, a transistor Q1 which is connected between the virtual power supply line VDD1 and a power supply line VDD and has a high threshold voltage, and a transistor Q2 which is connected between the virtual ground line VSS1 and a ground line VSS and has a low threshold voltage.
In the operation (active), the both transistors Q1 and Q2 are turned on, and a power supply voltage is supplied to the Low-Vth block 1. Since the Low-Vth block 1 is constituted by a transistor having a low threshold voltage, it operates at a high speed.
On the other hand, in the standby mode, the both transistors Q1 and Q2 are turned off, and a leak path extending from the power supply line to the ground line is shut off, thereby reducing the leak electric current.
However, since the ON resistance exists in the transistors Q1 and Q2 illustrated in FIG. 9, the potential of the virtual power supply line and the virtual ground line tends to be unstable in active state, and the circuit operation of the entire Low-Vth block 1 also becomes unstable.
Further, when the Low-Vth block 1 is active, since the leak electric current flows from the power supply line to the ground line through the leak path, it is difficult to reduce the leak electric current in this period. Furthermore, since a transistor having a high threshold voltage must be added besides the Low-Vth block 1, a circuit area increases, and data held in a flip flop or a latch in the Low-Vth block 1 is disadvantageously lost in the standby mode.
On the other hand, in order to minimize these problems, there is proposed such a circuit as shown in FIG. 10 in which only some cells in the logic circuit are replaced with transistors having a low threshold voltage. A heavy line in FIG. 10 indicates a cell constituted by using transistors having a low threshold voltage.
However, when each of some cells is constituted by transistors having a low threshold voltage as shown in FIG. 10, since the leak electric current flows to this cell, it is impossible to satisfy a demand to reduce the consumption power as much as possible in the standby mode (waiting period) as in a mobile phone and the like.
In view of the above-described problems, it is an object of the present invention to provide a semiconductor integrated circuit, a logic operation circuit and a flip flop capable of performing high-speed operation and have a leak electric current reduced.
To achieve this object, according to the present invention, there is provided a semiconductor integrated circuit comprising: a plurality of gate circuits; and a control circuit configured to control the operation of some gate circuits among the plurality of gate circuits, each of some gate circuits among the plurality of gate circuits including: a logic circuit constituted by a plurality of first transistors; and a switch circuit which can switch whether a power supply voltage is supplied to the logic circuit, is constituted by a second transistor having a threshold voltage higher than that of the first transistor, and is controlled by the control circuit.
According to the present invention, since only some gate circuits in the semiconductor integrated circuit are constituted by using transistors having a low threshold voltage, the speed of, e.g., only a part that accurate timing is required can be increased by using the transistors having a low threshold voltage, and any other part can be constituted by using the transistors having a reduced leak electric current and a high threshold voltage. As a result, both increase in speed and reduction in consumption power can be achieved.
Moreover, all the gate circuits in the semiconductor integrated circuit are constituted by transistors having a high threshold voltage and a low threshold voltage in the conventional MT-CMOS circuit, whereas only part of the gate circuits (for example, only a gate circuit on a critical path) is constituted by transistors having a high threshold voltage and a low threshold voltage in the present invention. Therefore, a device forming area of the circuit can be reduced as compared with the prior art MT-CMOS circuit, thereby attaining high integration.
In addition, according to the present invention, there is provided a logic operation circuit comprising: a gate circuit constituted by a plurality of first transistors; and a second transistor which is connected between a second reference voltage line and the virtual voltage line and has a threshold voltage higher than that of the first transistor, a source/drain terminal of the first transistor in the gate circuit being connected to either a source/drain terminal of another first transistor in the gate circuit or an output terminal of the gate circuit.
Additionally, according to the present invention, there is provided a logic operation circuit comprising: a gate circuit which is connected between a first reference voltage line and a virtual voltage line and constituted by a plurality of first transistors; and a second transistor which is connected between the virtual voltage line and a second reference voltage line and has a threshold voltage higher than that of the first transistor; and a third transistor which is connected between the first reference voltage line and an output terminal of the gate circuit and has a threshold voltage higher than that of the first transistor, the second and third transistors being on/off-controlled in such a manner that one of them is turned on while the other is turned off and vice versa.
Further, according to the present invention, there is provided a logic operation circuit comprising: a gate circuit constituted by a plurality of first transistors and connected to first and second virtual voltage lines; a second transistor which is connected between a first reference voltage line and the first virtual voltage line and has a threshold voltage higher than that of the first transistor; a third transistor which is connected between a second reference voltage line and the second virtual voltage line and has a threshold voltage higher than that of the first transistor; and a storage circuit capable of holding output logic of the gate circuit, the second and the third transistors being controlled to be OFF when the storage circuit holds the output logic of the gate circuit, and the second and third transistors being controlled to be ON when the storage circuit does not hold the output logic of the gate circuit.
Furthermore, according to the present invention, there is provided a logic operation circuit comprising: a gate circuit which is constituted by a plurality of first transistors and connected to first and second virtual voltage lines; a second transistor which is connected between a first reference voltage line and the first virtual voltage line and has a threshold voltage higher than that of the first transistor; a third transistor which is connected between a second reference voltage line and the second virtual voltage line and has a threshold voltage higher than that of the first transistor, and a bypass circuit which is connected to the gate circuit in parallel and constituted by a circuit which is substantially equal to the gate circuit by using a plurality of fourth transistors having a threshold voltage higher than that of the first transistor, the bypass circuit being connected between the first and second reference voltage lines.